Phase change memory (PCM) devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device, PRAM (phase-change random access memory), uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “SET state” and the amorphous state is referred to as a “RESET state”. Accordingly, a memory cell in a PRAM stores a logical ‘0’ by setting a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘1’ by setting the phase change material to the amorphous state.
The phase change material in a PRAM is converted to the amorphous state by heating the material to a first temperature above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at a second temperature lower than the melting temperature but above a crystallizing temperature for a sustained period of time. Accordingly, data is programmed to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described above.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), known in the art as a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling. In addition to, or as an alternative for the GST compound, a variety of other compounds can be used in the phase change material. Examples of the other compounds include, but are not limited to, 2-element compounds such as GaSb, InSb, InSe, Sb2Te3, and GeTe, 3-element compounds such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe, or 4-element compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Tesi Ge15Sb2S2.
The memory cells in a PRAM are called “phase change memory cells”. A phase change memory cell typically comprises a top electrode, a phase change material layer, a bottom electrode contact, a bottom electrode, and an access transistor. A READ operation is performed on the phase change memory cell by measuring the resistance of the phase change material layer, and a PROGRAM or WRITE operation is performed on the phase change memory cell by heating and cooling the phase change material layer as described above.
FIG. 1 is a circuit diagram illustrating a conventional phase change memory cell with MOS Switch Cell (or memory cell) 10 and a conventional diode type phase change memory cell 20. Referring to FIG. 1, memory cell 10 includes a phase change resistance element 11 comprising the GST compound, and a negative metal-oxide semiconductor (NMOS) transistor 12. Phase change resistance element 11 is connected between a bit line (BL) and NMOS transistor 12, and NMOS transistor 12 is connected between phase change resistance element 11 and ground. In addition, NMOS transistor 12 has a gate connected to a word line (WL).
NMOS transistor 12 is turned on in response to a word line voltage applied to word line WL. Where NMOS transistor 12 is turned on, phase change resistance element 11 receives a current through bit line BL. Phase change resistance element 11 is connected between bit line BL and the drain terminal of the NMOS transistor 12 in FIG. 1.
Referring again to FIG. 1, memory cell 20 comprises a phase change resistance element 21 connected to a bitline BL, and a diode 22 connected between phase change resistance element 21 and a wordline WL.
Phase change memory cell 20 is accessed by selecting wordline WL and bitline BL. In order for phase change memory cell 20 to work properly, wordline WL must have a lower voltage level than bitline BL when wordline WL is selected so that current can flow through phase change resistance element 21. Diode 22 is forward biased so that if wordline WL has a higher voltage than bitline BL, no current flows through phase change resistance element 21. To ensure that wordline WL has a lower voltage level than bitline BL, wordline WL is generally connected to ground when selected.
In FIG. 1, phase change resistance elements 11 and 21 can alternatively be broadly referred to as “memory elements” and NMOS transistor 12 and diode 22 can alternatively be broadly referred to as “select elements”.
The operation of phase change memory cells 10 and 20 is described herein below with reference to FIG. 2. In particular, FIG. 2 is a graph illustrating temperature characteristics of phase change resistance elements 11 and 21 during programming operations of memory cells 10 and 20. In FIG. 2, a reference numeral 1 denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the amorphous state, and a reference numeral 2 denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the crystalline state.
Referring to FIG. 2, in a transition to the amorphous state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for a duration T1 to increase the temperature of the GST compound above a melting temperature Tm. After duration T1, the temperature of the GST compound is rapidly decreased, or “quenched”, and the GST compound assumes the amorphous state. On the other hand, in a transition to the crystalline state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for an interval T2 (T2>T1) to increase the temperature of the GST compound above a crystallization temperature Tx. At T2, the GST compound is slowly cooled down below the crystallization temperature so that it assumes the crystalline state.
A phase change memory device typically comprises a plurality of phase change memory cells arranged in a memory cell array. Within the memory cell array, each of the memory cells is typically connected to a corresponding bit line and a corresponding word line. For example, the memory cell array may comprise bit lines arranged in columns and word lines arranged in rows, with a phase change memory cell located near each intersection between a column and a row.
Typically, a row of phase change memory cells connected to a particular word line is selected by applying an appropriate voltage level to the particular word line. For example, to select a row of phase change memory cells similar to phase change memory cell 10 illustrated in the left side of FIG. 1, a relatively high voltage level is applied to a corresponding word line WL to turn on NMOS transistor 12. Alternatively, to select a row of phase change memory cells similar to phase change memory cell 20 illustrated in the right side of FIG. 1, a relatively low voltage level is applied to a corresponding word line WL so that current can flow through diode 22.
Unfortunately, conventional PRAM devices can receive several bits of input at the same time but are unable to simultaneously program the bits into corresponding memory cells. For example, a PRAM may receive 16 inputs through a plurality of pins, but the PRAM may not be able to simultaneously access 16 phase change memory cells. One reason for this shortcoming is that if a current of 1 mA is required to program one phase change memory cell, then a current of 16 mA would be required to simultaneously program 16 phase change memory cells. Moreover, if the efficiency of a driver circuit providing the current is 10%, then a current of 160 mA would be required to simultaneously program the 16 memory cells. However, conventional PRAM devices are generally not equipped to provide currents with such high magnitudes.
A paper by Samsung of Hwasung, Korea (“A 0.1 μm 1.8V 256 Mb 66 MHz Synchronous Burst PRAM”, 2006 IEEE International Solid-State Circuits Conference 1-4244-0079-1/06) shows a write mode selector, which can determine the write data width ranging from X2 to X16 depending on the operating environment. If the write performance is more important and the system power can support 16 mA, the X16 mode would be selected. In other cases, smaller write data width will help reduce the total peak power and average operating power. Another approach to resolve a high current requirement for RESET programming, even with an external pin driving method, has also been proposed by Samsung (“A 90 nm 1.8V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput”, IEEE Journal Of Solid-State Circuits, VOL. 43, NO. 1, January 2008). However, this method is manually selected by the user and does not provide an automated and optimized way to improve the total write performance and reduce power consumption.
Another approach is to use data comparison write (DCW), which reduces the write power (“A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme”, Byung-Do Yang, et al., IEEE International Symposium on Circuits and Systems, May 2007). The DCW circuit reads stored values from PCM cells during write operation, and then it writes into the PCM cells where the input and stored values are different. If the PCM cell value does not change, it does not consume write power.
FIG. 3 shows a flowchart of the data comparison write (DCW) scheme. The DCW scheme performs the READ (RD) operation before the WRITE (WR) operation to determine the previously stored value in the selected PCM cell. If the input and stored values are the same, no WRITE operation is performed. This comparison is done with bit-based comparison. Only different bit write data is programmed into the PCM cell. This way, the DCW scheme does not consume the write power for two cases (0→0, 1→1). Therefore, the average power consumption is given by (Pset+Preset)/4, where Pset is the power consumed for the SET operation and Preset is the power consumer for the RESET operation. However, most of the data inputs are random patterns so the situations where power is reduced is minimal. Additionally, there are no power savings for maximum RESET programming cases where all data pattern undergo a transition in the same cycle.
Another approach is to use a data inversion scheme (“A Low Power PRAM using a Power-Dependant Data Inversion Scheme”, Byung-Do Yang et al., 2nd International Conference on Memory Technology and Design, May 7-10, 2007, Giens, France). This approach requires one additional polarity bit for the write data to determine whether or not all bits should be inverted.